1. Field of the Invention
The present disclosure relates to switches and, in particular, to metal oxide semiconductor (MOS) switches.
2. Description of the Related Art
Clock bootstrapping (“bootstrapping”) is a technique used to enhance the linearity of Metal-Oxide-Semiconductor (MOS) switches. Through bootstrapping, the gate voltage of a MOS switch during the ON state is set at a constant value larger than the supply voltage or at a constant offset value relative to the input signal, both achieving a large gate overdrive voltage (gate source voltage minus the switch on/off threshold voltage). In the former, the gate overdrive voltage is variable, whereas in the latter it is constant (signal independent). The result is lower and more linear switch impedance, thus enabling the sampling of an analog signal with greater precision.
High-speed pipeline analog-to-digital converters (ADC's) make use of bootstrapping techniques. Pipeline analog-to-digital converters (ADCs) are sub-ranging data converters in which a signal is quantized coarsely in several steps and the results of the different steps are then combined to achieve a high level of quantization accuracy.
Referring to FIG. 1A, a typical pipeline ADC 10 includes a plurality of stages 12, 14, . . . , L. In the first stage 12, the input Vin is converted using a flash ADC (not shown) and is combined with results from the subsequent stages 14, 16, . . . , L to form an output. The error in each stage is determined by converting the output of that stage using a digital-to-analog converter. The difference between the input to the stage and the error is the “residue.” The residue for each stage is amplified and fed to the next stage and converted in the same fashion in the next stage. The output of the last stage L is provided to a backend ADC 16 which resolves the last bits. All outputs may be provided for time alignment and digital error correction 20.
As shown in FIG. 1B, a typical stage in a pipeline ADC comprises an input signal sampling network 103a, a coarse flash ADC 102 with its own sampling network 103b, a DAC 104, and an amplifier 106. The sampling network and flash ADC 102 sample a first input signal 108 with switches 101a, 101b at the same time. The ADC 102 provides a digital version of the signal to the DAC 104. The DAC 104 converts the digital version of the signal back into analog form, providing a second signal which is subtracted 110 from the first input signal 108. The result is the “residue” and is amplified in order to occupy, typically and in the absence of errors, a portion of the range of the following stage, for example half. Ideally, the residue consists only of quantization noise.
If the sampling network 103a and flash ADC 102 do not sample the same value of the first input signal 108, the residue contains a signal-dependent component instead of quantization error only. This error term varies (increases) with the input signal frequency and, since it occupies part of the amplifier output range, it can lead to premature overload of the ADC 102.
Accordingly, it is desirable to match the main sampling network to that within the flash ADC. By “matching” it is meant not only matching the sampling time instants but also matching the time constants. To achieve the best possible matching, the two networks should be nearly identical or one a linearly scaled version of the other (including parasitics) and the switches 101a, 101b driven identically. Sampling time should be maximized to eliminate residual transient effects from the action of closing the switch, providing more accurate tracking of the input signal 108. This may be more important when the ADC 102 clock rate exceeds 300 MHz.
FIG. 2A and FIG. 2B indicate exemplary embodiments of a prior art bootstrapping technique whereby the switch gate-source voltage is constant. In the technique of FIG. 2A (referred to as “lumped” bootstrapping), a single bootstrapping circuit 202 drives the switches 101a, 101b in the input and flash ADC sampling networks 103a, 103b. The circuit further includes capacitors C1, C2 and switches 204a-204d and switches 206a, 206b. The switches are driven by periodic clocks denoted phase 1, phase 2. When phase 1 is true, phase 2 is false and vice versa. When phase 1 is true, the capacitors C1, C2 are charged to the voltage Vin. When phase 2 is true, the capacitors are connected to the sampling networks.
In the technique of FIG. 2B (referred to as “distributed” bootstrapping), each switch 101a, 101b is provided with its own bootstrapping circuit 202a, 202b, respectively. The circuit also includes capacitors C3, C4 and switches 208a-208d and switches 210a, 210b. In general, the circuit functions to charge the capacitors C3, C4 similarly to that of FIG. 2A.
Bootstrapping circuits typically employ thick oxide devices in specific locations to handle large (above supply) voltages without experiencing break down. Such devices require physical dimensions much larger than the minimum dimensions practiced for low voltage devices. Thick oxide devices may also have higher threshold voltage and lower transconductance values. For these reasons, thick oxide devices behave poorly both as active devices and as switches. When used in bootstrapping circuits, they function as switches.